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Espressif Systems /ESP32-S3 /SENSITIVE /CORE_0_VECBASE_OVERRIDE_1

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Interpret as CORE_0_VECBASE_OVERRIDE_1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE0CORE_0_VECBASE_OVERRIDE_SEL

Description

core0 vecbase override configuration register 1

Fields

CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE

world0 vecbase_override register, when core0 in world0 use this register to override vecbase register.
CORE_0_VECBASE_OVERRIDE_SEL

Set 0x3 to sel vecbase_override to override vecbase register.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data